1. Field of the Invention
The present invention relates to a method for programming a plurality of memory cells of a nonvolatile semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are devices in which data can be stored and from which stored data can be retrieved. Semiconductor memory devices can be classified into volatile memory and nonvolatile memory. The volatile memory needs a power supply to retain data while the nonvolatile memory can retain data even when power is removed. Therefore, nonvolatile memory devices have been widely used in applications in which power can be interrupted suddenly.
Nonvolatile memory devices comprise electrically erasable and programmable ROM cells, known as flash EEPROM cells. FIG. 1 shows a vertical cross-section of the flash EEPROM cell 10. Referring to FIG. 1, a deep n-type well 12 is formed in a bulk region or a P-type substrate 11, and a p-type well 13 is formed in the n-type well 12. An N-type source region 14 and an N-type drain region 15 are formed in the P-type well 13. A p-type channel region is formed between the source region 14 and the drain region 15. A floating gate 17, which is insulated by an insulating layer 16, is formed on the P-type channel region. A control gate 19, which is insulated by another insulating layer 18, is formed on the floating gate 17.
FIG. 2 shows threshold voltages of the flash EEPROM cell 10 during program and erase operations. Referring to FIG. 2, the flash EEPROM cell 10 has a higher threshold voltage range (about 6 to 7V) during the program operation, and has a lower threshold voltage range (about 1 to 3V) during the erase operation.
Referring to FIGS. 1 and 2, during the program operation, hot electrons need to be injected from the channel region adjacent to the drain region 15 to the floating gate electrode, so that the threshold voltage of the EEPROM cell increases. In contrast, during the erase operation, the hot electrons injected into the floating gate 17 during the program operation need to be removed, so that the threshold voltage of the EEPROM cell will decrease. Therefore, the threshold voltages of the EEPROM cell are varied after the program and erase operation.
FIG. 3 shows a block diagram of a prior art nonvolatile semiconductor memory device 30. Referring to FIG. 3, the memory device 30 comprises a memory array 32, a column decode and level shift circuit 34, a row decode and level shift circuit 36, an I/O circuit 38, and a pump circuit 39.
FIG. 4 shows a part of the memory array 32 of FIG. 3. Referring to FIG. 4, the memory array includes a plurality of word lines WL0 to WL2, a plurality of bit lines BL0 to BL7, and a plurality of memory cell transistors MX,Y arranged in the form of a matrix, wherein letters X and Y respectively stand for a cell position in the horizontal direction and a cell position in the vertical direction. The memory cell transistors MX,Y are connected to word lines in rows and to bit lines in columns. For example, a cell transistor M1,1 has a drain connected to the first bit line BL0 and has a gate connected to the first word line WL0, and a cell transistor M1,2 has a drain connected to the second bit line BL1 and has a gate connected to the first word line WL0.
Referring now to FIG. 3, the I/O circuit 38 receives address signals ADDRESS, data signals DATA, and a clock signal XCLK from a processor or memory controller (not shown). The column decode and level shift circuit 34 receives a column address AC from the I/O circuit 38 for selecting a single bit line from the memory array 32. The row decode and level shift circuit 36 receives a row address AR from the I/O circuit 38 for selecting a single word line from the memory array 32.
During a program operation, the pump circuit 39 receives a mode signal PGM from the I/O circuit 38 for generating pumped output voltages to the circuits 34 and 36. In response to the column address AC, the circuit 34 provides the pumped output voltage to the selected bit line. In response to the row address AR, the circuit 36 provides the pumped output voltage to the selected word line.
FIG. 5 shows a plot of voltage and current waveforms versus time of a typical prior art programming operation. Referring to FIG. 4 and FIG. 5, four memory cell transistors M1,1, M1,2, M1,3, and M1,4 in FIG. 4 are selected to be programmed in response to a column address AC and a row address AR. At time t0, the pump circuit 39 generates a pumped output voltage VC having a level higher than a power supply VDD (e.g., 1.8VDC) and provides the high voltage (e.g., 4VDC) to the drains of the selected memory cell transistors through the bit lines. Upon receiving the pumped voltage VC, the total current IC flowing through the selected memory cell transistors increases to about 220 μA. The voltage VC is maintained at its high level until a time t1 is reached. At time t1, the total current IC flowing through selected memory cell transistors reduces to about 50 μA. After the time t1, the pump circuit 39 stops its operation, and a level of its output voltage VC drops to the power supply VDD. The time period t0 to t1 shown in FIG. 5 is the pulse width, which is the effective time duration for the programming operation. In this example, the time period t0 to t1 is about 1 μS.
As shown in FIG. 5, four memory cell transistors are selected to be programmed during the time period t0 to t1, so that the instant current of about 220 μA is required for the program operation. Presently, semiconductor memory devices have become highly integrated. More than tens of thousands of memory cells are integrated into a single semiconductor memory device so that much more data can be stored. To program a 16K-bit memory device comprising an array of 128×128 memory cells, relatively large amounts of power is required during the operation and the duration of the entire program can be rather long. In order to solve the foregoing problems, there is a need to provide an improved programming method.